In order to realize ultra-high density DRAM's, it is clear that new memory cell structures and array designs are needed. Prior art configurations do not meet projected cell density requirements for 256 megabits and higher. Prior art cell structures have, in a number of cases, employed three dimensional cell structures to enable denser cell structures. Some of those cell configurations have included memory capacitors formed in trenches, vertically oriented wordlines having high aspect ratio cross-sections, and vertically oriented access transistor structures.
In FIG. 1, a widely used DRAM configuration is shown wherein each cell 10 includes an access transistor 12, storage capacitor 14, bitline 16, wordline 18, and passing wordline 20. The gate of transistor 12 is connected to wordline 18 and the source of transistor 12 is connected to bitline 16. Application of appropriate potentials to bitline 16 and wordline 18 enables data to be either written into or read from capacitor 14 in the known manner. The circuit arrangement shown in FIG. 1 is termed a "folded bitline" structure as the output from cell 10 is supplied across terminals 22 and 24, to a differential sense amplifier, and cell 10 is traversed by both the connected wordline 18 and the passing wordlne 20.
The remaining DRAM cells in FIG. 1 are identical, with passing wordlines 20 and 26 controlling memory cells in rows 24 and 30, and wordlines 18 and 32 controlling the alternate row cells.
In FIG. 2, a planar view of an exemplary structure of a cell 10 and in FIG. 3 a section, taken along line 3--3 of the cell of FIG. 2 is illustrated. In FIGS. 2 and 3, it can be seen that wordline 18 forms the gate structure of transistor 12, whereas passing wordline 20 rests upon thick oxide layer 36 and does not affect the operation of cell 10. Bitline 16 is connected via stud 38 to source 40 of transistor 12. Drain 42 connects to trench capacitor 44 (via contact strap 41) which is, in turn, formed in substrate 46. Prior art references disclosing DRAM cells that use various aspects of the cell arrangement shown in FIGS. 2 and 3 can be found in U.S. Pat. Nos. 4,688,063 to Lu et al., 4,798,794 to Ogura et al. and 4,734,384 and 4,922,313 to Tsuchiya.
High density DRAM cell structures can be found in U.S. Pat. No. 4,873,560 to Sunami et al. and in U.S. Pat. No. 4,916,524 to Teng et al. In the Sunami et al. patent (see FIG. 27 of Sunami et al.), vertically oriented wordlines and passing wordlines are employed with each cell having an in-trench, vertically oriented access transistors. The drain of each vertical access transistor in Sunami et al. connects to the trench capacitor via an opening in the insulating layer in the trench's side wall. In the Teng et al. patent, a wordline has a T shaped portion that makes contact with the gate of a vertical access transistor emplaced above a trench capacitor. As in Sunami et al., the access transistor of Teng et al. exhibits a drain which connects to a contact of the trench capacitor via an opening in the insulating layer of the trench's sidewall.
Notwithstanding the innovations shown in the above-noted prior art, additional structural compaction of access transistors and trench capacitors is required to enable ultra-high DRAM densities to be achieved. Furthermore, even where vertically oriented access transistors are employed, care must be taken to assure that a reliable, wide-area contact is maintained between the drain of the access transistor and the trench capacitor's internal contact.
Accordingly, it is an object of this invention to provide an ultra-dense packing arrangement for a DRAM memory cell.
It is another object of this invention to provide an ultra-dense DRAM structure which makes use of planar-oriented access transistors.
It is still another object of this invention to provide an ultra-dense DRAM structure which makes use of vertically oriented access transistors, wherein drain/trench capacitor contact is enhanced.
It is yet another object of this invention to provide an improved method for constructing an ultra-dense DRAM structure.